In recent years, chip scale packaging technologies for packaging the individual chip at wafer-level in accordance with the requirements for high integration, weight lightening, thickness reduction, shortening the length and miniaturization of the semiconductor package have been applied to the related art field.
As one example of the chip scale packaging technologies, there is a Wafer Level Fan-In Package of which input/output terminals such as solder balls for transmitting an electric signal within a section of the respective chip are connected thereto. Another such case is Wafer Level Fan-Out Package of which a conductive line can extend to a peripheral portion of the respective chip by using a separate interposer, etc. and input/output terminals are melted and attached to the extended portion of the conductive line.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.